The present invention relates to a MOS DRAM. More particularly, it relates to a trench capacitor cell structure well suited to microminiaturization and also to a method of applying a voltage thereto.
DRAMs have realized a rise in the density of integration to about four times in a matter of three years, wherein the mainstream thereof has already shifted from 64 k-bits to 256 k-bits. Even DRAMs of 1 M-bits will soon be mass-produced. The heightened integration has been achieved chiefly by the scaling-down of device sizes. The decrease of a storage capacitance attendant upon the scaling-down, however, has posed the problems of degradation in a signal-to-noise ratio, storage charge destruction ascribable to alpha-particles, and so on. As measures to be taken against these problems, a large number of trench capacitor cell designs have been published. Among them, one proposed by Shimizu and 9 others in "BSD Cell for Megabit-class DRAM"; the Institute of Electronics and Communication Engineering of Japan, Group for the Research of Semiconductors and Transistors, SSD86-2, p. 9, is immune against alpha-particles and is considered promising. This cell has a structure shown in FIG. 1. In this cell, a charge storage node 24 is formed inside a trench provided in the surface of a semiconductor, in a manner to be surrounded with a capacitor insulator 23. That is, storage charges are insulated from the semiconductor substrate substantially perfectly. Therefore, even when electrons and holes are generated within the semiconductor substrate by the cause of alpha-particles, they seldom gather to the storage node. Accordingly, the cell has the feature that the storage charge destruction is less prone to occur.
Although the memory cell structure has the excellent feature as described above, it is not suited to CMOS (Complementary Metal Oxide Semiconductor) devices which form the mainstream of present-day LSI. More specifically, a thin p.sup.- epitaxial layer 22 is indispensable to this memory cell structure. Nevertheless, this part becomes a high-concentration-p layer because p.sup.+ impurity atoms diffuse upwards in a high temperature process during the formation of wells required for the CMOS device.
As stated above, in the CMOS implementation, it has been technically difficult to employ a p.sup.- -on-p.sup.+ type semiconductor substrate having a thin epitaxial layer.